A liquid crystal display device is widely used as a display device of a TV, a monitor of a personal computer etc. Particularly, a liquid crystal display device having a switching element such as a thin film transistor (hereinafter also referred to as a TFT) offers superior image display even with a larger number of display pixels, without causing crosstalk between adjacent display pixels.
FIG. 5 shows this type of liquid crystal display device. The major part of the device includes a liquid crystal display panel 1 and a driving circuit section. The liquid crystal display panel 1 is made up of a pair of electrode substrates and a liquid crystal composition held between the substrates. Each external surface of the electrode substrates is covered with a polarizing plate.
One of the electrode substrates is a TFT array substrate on which a plurality of signal lines S(1), S(2), . . . S(i), . . . S(N), and a plurality of scanning signal lines G(1), G(2) . . . G(j), . . . G(M) are formed on a transparent insulation substrate 100 made of a glass or the like in a matrix manner. Further, a switching element 102 made of a TFT connected to a pixel electrode 103 is formed on each of the intersections of the signal lines and the scanning lines. The insulative substrate 100 provided with such elements are entirely covered by an alignment film to function as a TFT array substrate.
The other electrode substrate is a counter substrate. As with the TFT array substrate, the counter substrate includes a transparent insulation substrate made of a glass or the like, the entire surface of which is covered with a counter electrode 101 and an alignment film laminated on each other. Further, the scanning signal lines of the display panel are connected to a scanning signal line driving circuit 300, the signal lines are connected to a signal line driving circuit 200, and the counter electrode is connected to a counter electrode driving circuit COM. These sections form the driving circuit section.
FIG. 6 shows an example of the scanning signal line driving circuit (gate driver) 300. This example is made up of a shift register section 3a having M flip-flops connected in a cascade manner, and a selection switches 3b that are operated according to the output of each flip-flop.
One of the input terminals VD 1 of each selection switch 3b is supplied with a gate-ON-voltage to turn on a TFT 102 (see FIG. 5), while the other input terminal VD2 is supplied with a gate-OFF-voltage to turn off the TFT 102. Therefore, a data signal (GSP) is sequentially transferred to each flip-flop in response to a clock signal (SCK), and then sequentially outputted to each selection switch 3b. Accordingly, the selection switch 3b outputs a voltage Vgh to turn on the TFT for 1 scanning period (TH) to the corresponding scanning signal line 105, and after the scanning period, outputs a voltage Vgl to turn off the TFT to the same scanning signal line 105. With this operation, a video signal outputted to each signal line 104 (see FIG. 5) from the signal line driving circuit 200 is written to a corresponding pixel.
FIG. 7 is an equivalent circuit diagram of a display pixel P(i, j) of a structure in which a pixel capacitor Clc and an auxiliary capacitor Cs are connected in parallel to a counter potential VCOM of a counter electrode driving circuit COM. In the figure, Cgd expresses a parasitic capacitor between gate-drain of the TFT.
FIG. 8 is a driven waveform chart of a conventional liquid crystal display device. In the figure, Vg expresses a waveform of a scanning signal line, Vs expresses a waveform of 1 signal line, and Vd expresses a drain waveform.
Here, a conventional driving method is explained below with reference to FIGS. 5, 7 and 8. Note that, it is widely known that the liquid crystal needs to be driven by alternating driving to prevent burnt image-lag or degradation of display. Accordingly, the following conventional driving method is explained using a frame inversion driving, an exemplary one of the alternating driving methods.
As shown in FIG. 8, in the first field, the scanning voltage Vgh is supplied from the scanning signal line driving circuit 300 to the gate electrode g(i, j) (see FIG. 5) of the TFT of a display pixel P(i, j), and the TFT turns on. As a result, the video signal voltage Vsp from the signal line driving circuit 200 is written to a pixel electrode via the source electrode and the drain electrode of the TFT. The pixel electrode holds the pixel potential Vdp until the scanning voltage Vgh is supplied in the next field (TF2), as shown in FIG. 8. Since the counter electrode is kept at a predetermined pixel potential Vdp by the counter electrode driving circuit COM, the liquid crystal composition held by the pixel electrode and the counter electrode responds according to the potential difference between the pixel potential Vdp and the counter potential VCOM, thereby displaying an image.
Similarly, as shown in FIG. 8, when the scanning voltage Vgh is supplied from the scanning signal line driving circuit 300 to the gate electrode g(i, j) of the TFT of a display pixel P(i, j) in the second field (TF1), the TFT turns on, and the video signal voltage Vsn from the signal line driving circuit 200 is written to a pixel electrode. The pixel electrode holds the pixel potential Vdn, and the liquid crystal composition responds according to the potential difference between the pixel potential Vdn and the counter potential VCOM, thereby displaying an image, and realizing liquid crystal alternating driving.
Further, as shown in FIG. 7, each TFT has a structure indispensably including a parasitic capacitor Cgd between gate and drain. Therefore, as shown in FIG. 8, a level shift ΔVd is caused in the pixel potential Vd at a fall of the scanning voltage Vgh due to the parasitic capacitor Cgd. The level shift ΔVd caused in the pixel potential Vd at a fall of the scanning voltage Vgh due to the parasitic capacitor Cgd can be expressed as ΔVd=Cgd·(Vgh−Vgl)/(Clc+Cs+Cgd) where Vgl denotes a non-scanning voltage (OFF-voltage of the TFT) of the scanning signal. This level shift causes a problem of flicker or degradation of display of the displayed image, and therefore unwanted for a liquid crystal display device aimed at further improving definition and quality.
In view of this problem, there has been a conventional method of applying a bias voltage to the counter electrode potential VCOM of the counter electrode, in order to reduce the level shift ΔVd caused by the parasitic capacitor Cgd in advance.
However, in the foregoing conventional method, when forming the scanning signal lines G(1), G(2) . . . G(j), . . . G(M) on a transparent insulation substrate 100 made of a glass or the like as in FIG. 5, there are some difficulties of forming those scanning lines with ideal wiring that is free from a signal propagation delay characteristic. Therefore, it is unavoidable the scanning signal lines become signal propagation delay paths that cause the signal propagation delay characteristic to some extent.
FIG. 10 is a propagation equivalent circuit diagram for showing a signal propagation delay characteristic in a single scanning signal line G(j). In FIG. 10, rg1, rg2, rg3, . . . rgN mainly express a resistance component of the wiring material forming the scanning signal line, and a resistance component due to the wiring width and the wiring length. Further, cg1, cg2, cg3, . . . cgN are various parasitic capacitors that are in capacitive coupling relation to the scanning signal line in this structure. Each of the parasitic capacitors are made of such as a cross capacitor that is generated by intersection with the signal line. As described, the scanning signal line is a distributed-constant type signal propagation delay path.
FIG. 11 is an explanatory view illustrating a state where a scanning signal VG(j) supplied from the scanning signal line driving circuit onto the scanning signal line is becoming blunt inside the panel, due to the signal propagation delay characteristic. In the figure, the waveform Vg(1, j) denotes a waveform in the vicinity of the gate g(1, j) immediately after the output from the scanning signal line driving circuit 300. Bluntness can be hardly seen in this waveform. In contrast, in the same figure, the waveform Vg(N, j) denotes a waveform in the vicinity of the gate g(N, j) at the terminating end of the scanning signal line. This waveform is blunt due to the signal propagation delay characteristic of the scanning signal line. This waveform bluntness causes a variation amount SvN per unit time.
Further, the TFT is not an absolute ON/OFF switch, as it has a V-I characteristic (gate voltage-drain current characteristic) shown in FIG. 9. In the figure, the horizontal axis denotes a voltage supplied to the gate of the TFT, while the vertical axis denotes a drain current. Generally, the scanning pulse has a voltage level Vgh that is sufficient to turn on the TFT, and a voltage level Vgl that is sufficient to turn off the TFT. However, the scanning pulse also has an intermediate ON area (linear area) between the threshold value VT of TFT and the Vgl level.
Therefore, as shown in FIG. 11, in the pixel at the gate g(1, j) immediately after the scanning signal line driving circuit 300, the waveform rapidly falls from the Vgh level to the Vgl level of the scanning signal. Therefore, there is no influence of the characteristic in the linear area of the TFT, and therefore, it is possible to approximate the level shift ΔVd(1) caused by the parasitic capacitor Cgd to ΔVd(1)=Cgd·(Vgh−Vgl)/(Clc+Cs+Cgd).
However, in the pixel in the vicinity of gate g(N, j) at the terminating end of the scanning signal line, there is bluntness of a falling waveform of the scanning signal. Thus, the linear area characteristic of the TFT, and the level shift is caused at the pixel potential Vd due to the parasitic capacitor Cgd not occurring during a time where the scanning signal falls from the Vgh level to around the threshold level VT in which the TFT is ON in the linear manner. However, the level shift ΔVd(N) is caused at the pixel potential Vd(N, j) due to the parasitic capacitor Cgd during a time where the scanning signal varies from the threshold potential Vd to the Vgl level. Accordingly, the level shift ΔVd(N) is expressed as ΔVd(N)<Cgd·(Vgh−Vgl)/(Clc+Cs+Cgd), thereby satisfying ΔVd (1)>ΔVd(N).
As in the foregoing example, the level shift ΔVd that occurs in the pixel potential Vd due to the parasitic capacitor Cgd is not uniform in the display screen. Therefore, it becomes more significant in a larger screen or high-definition display.
Accordingly, the conventional method using a bias of the counter electrode cannot cancel the unevenness of the level shift in the display screen. Thus, the pixels cannot be driven by the optimum alternating driving, thereby inducing some defects, such as flicker, or burnt image-lag due to application of DC component.
Japanese Patent Publication No. 3406508 (published on Oct. 15, 1999) (U.S. Pat. No. 6,359,607B1) discloses an invention intended to solve such a conventional problem. This patent document discloses a display device and method in which the scanning signal has such a falling waveform, when outputted to the scanning signal line, that it falls with a slope from an ON-level of the switching element, and then falls substantially vertically before reaching the OFF-level of the switching element. With this arrangement, the invention of the patent document successfully reduce occurrence of flicker etc. caused by fluctuation of pixel potential due to the parasitic capacitor.
Further, even though the wiring formed on the transparent insulation substrate made of a glass or the like is not an ideal wiring path free from signal delay but a signal delay path causing some signal delay, the foregoing invention cancels display unevenness due to the signal delay. It further reduces and equalizes a level shift that occurs at a pixel potential due to the parasitic capacitor. As a result, the image display can be performed with higher definition and quality.